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Model :
SKU : DM-KINGSTON ECC 64GB 6400
KSM64R52BD4-64MD
64GB 2Rx4 8G x 80-Bit
PC5-6400 CL52 Registered EC8 288-Pin DIMM
DESCRIPTION
Kingston's KSM64R52BD4-64MD is a 8G x 80-bit (64GB)
DDR5-6400 CL52 SDRAM (Synchronous DRAM), 2Rx4, ECC,
memory module, based on forty 4G x 4-bit FBGA components. The
SPD is programmed to JEDEC standard latency DDR5-6400 timing
of 52-52-52 at 1.1V. Each 288-pin DIMM uses gold contact fingers.
The electrical and mechanical specifications are as follows:
FEATURES
• Power Supply: VDD = 1.1V Typical
• VDDQ = 1.1V Typical
• VPP = 1.8V Typical
• VDDSPD = 1.8V to 2.0V
• On-Die ECC
• x80 ECC (x40, 2 independent I/O sub channels)
• 32 internal banks
• Hard/Soft Post Package Repair
• Sideband access with I3C/I2C
• PCB: Height 1.23” (31.25mm)
• RoHS Compliant and Halogen-Free
• Performance / Technology
This SDRAM module operates at standard JEDEC latency timings of CL52 (52-52-52). By avoiding extreme overclocked latencies, Kingston guarantees the absolute rock-solid reliability required for machines that must run 24/7/365 without a reboot. The module is RoHS compliant, halogen-free, and utilizes premium gold contact fingers for long-term electrical conductivity.
• Compatibility / Use Cases
This memory is heavily validated for next-generation enterprise hardware [3807102986563752387]. It is the absolute optimal choice for upgrading high-end workstations running AMD Threadripper PRO 7000/9000 series, AMD EPYC servers, and Intel Xeon Scalable processors.
Attribute | Specification |
|---|---|
Brand | Kingston |
Series | Server Premier |
Part Number (MPN) | KSM64R52BD4-64MD |
Device Type | DDR5 Registered ECC DIMM (RDIMM) for Enterprise Servers & Workstations |
Form Factor | 288-Pin RDIMM (Gold contact fingers) |
Total Capacity | 64 GB |
Module Organization | 8G × 80-bit (Dual Rank, 2Rx4) |
Component Configuration | 40× 4G × 4-bit (16Gb) FBGA DRAM ICs |
DRAM Die / Vendor | Micron D-Die (denoted by the "MD" MPN suffix) |
Speed Rating | DDR5-6400 MT/s (PC5-51200 / PC5-6400) |
JEDEC Latency Profile | CL52-52-52 @ 1.1 V |
CAS Latency (tCL) | 52 Clock Cycles |
Row Active Time (tRAS min) | 32 ns |
Row Precharge Time (tRP min) | 16 ns |
Row Cycle Time (tRC min) | 48 ns |
Refresh to Active / Refresh Command Time (tRFC min) | 295 ns |
Supply Voltages | VDD: 1.1 V (Typical) VDDQ: 1.1 V (Typical) VPP: 1.8 V (Typical) VDDSPD: 1.8 V to 2.0 V |
Error Correction & Bus Width | Bus Architecture: 80-bit width (Two independent 40-bit sub-channels: 32-bit data + 8-bit ECC each) Sideband ECC: Multi-bit error detection and Single-Bit Correction (SEC-DED) On-Die ECC (ODECC): Internal DRAM array integrity |
Internal Bank Architecture | 32 Internal Banks (8 Bank Groups of 4 Banks each) |
Management & Telemetry Interface | High-speed I3C Basic & legacy I2C Serial Bus access via integrated SPD Hub / Thermal Sensor |
Fault Recovery & Servicing | Target Row Refresh (TRR), Hard Post Package Repair (hPPR), Soft Post Package Repair (sPPR) |
PCB Form Factor & Height | Standard Height: 1.23" (31.25 mm) |
Thermal & Operating Range | Operating (Tc): 0 °C to +95 °C Storage: -55 °C to +100 °C |
Safety & Environmental Standards | UL 94 V-0 Flammability Rating, RoHS Compliant, Halogen-Free |